When a clock generator in an electronic device generates a single frequency, emission increases at the frequency and higher harmonics. For this reason, use is made of a spread spectrum clock generator that reduces the peak of unnecessary emissions by frequency modulation and diminishes EMI (electromagnetic interference).
A PLL (phase-locked loop) in which a pulse-swallow frequency divider is provided in a feedback counter generally is used as a conventional spread spectrum clock generator of this kind (e.g., see M. Sugawara, T. Ishibashi, K. Ogasawara, M. Aoyama, M. Zwerg, S. Glowinski, Y. Kameyama, T. Yanagita, M. Fukaishi, S. Shimoyama, T. Ishibashi and T. Noma, “1.5 Gbps, 5150 ppm Spread Spectrum SerDes PHY with a 0.3 mW, 1.5 Gbps Level Detector for Serial ATA”, Symposium on VLSI Circuits Digest of Technical Paper 5-3, FIG. 1, June/2002). This PLL implements frequency modulation by affording two integers A and A-1 as divider ratios and switching between A and A-1. By changing the proportions of A and A-1 at predetermined fixed intervals, average frequency f is varied to thereby generate a spread spectrum clock.
With a PLL having a pulse-swallow frequency divider provided in a feedback counter, a single pulse of a step phase error enters the PLL as an input when the frequency divider is changed over. Since the PLL is in the negative feedback loop, a transient response is caused by the entered step phase error. It is expected that if the damping factor of the negative feedback loop is large, the clock frequency will vary out of specs owing to the transient response. If the damping factor is small, on the other hand, there is a possibility that the stability of the loop will be lost. Furthermore, since the characteristic of a spread spectrum clock generator is decided by control of the pulse-swallow frequency divider and the overall characteristic of transient response due to step phase error, a large number of design parameters exists and labor expended in optimizing design increases.
It should be noted that the PLL described in the above-cited reference is equipped with the pulse-swallow frequency divider and is so adapted that a smooth characteristic is obtained by using post-filtering. However, the reference is silent on information (measures) regarding a fluctuation in the PLL characteristic.
A spread spectrum clock generating circuit having a PLL, which is equipped with a plurality of program counters, and a frequency modulating circuit also is known [e.g., see the specification of Japanese Patent Kokai Publication No. JP-A-7-235862 (pages 9, 10 and FIGS. 6, 7, 8 and 9)].
Also known is a clock generating apparatus comprising a clock generator for generating m-phase clock signals having a phase difference between them; a selection processor for successively selecting one of the m-phase clock signals generated by the clock generator to thereby generate a second clock signal; and a dithering controller for supplying the selection processor with a control signal so that the phase of the second clock signal obtained from the selection processor will fluctuate within a prescribed range and the peak of a spectrum will be dispersed (e.g., see the specification of Japanese Patent Kokai Publication No. JP-P2001-148690A (pages 3 and 10 and FIGS. 3 and 11)]. The clock generating apparatus of this patent reference is equipped with a delay circuit or ring oscillator as the m-phase clock generator. FIG. 8 is a diagram illustrating the structure of the clock generator described in this patent reference, the generator using a ring oscillator 110 to generate a 5-phase clock. As shown in FIG. 8, five inverting delay circuits 111 to 115 are connected in ring form and clocks c0 to c4 of five phases are extracted from the outputs of the respective delay circuits via buffers 116 to 120, respectively. Reference numerals 121 to 125 denote frequency divider circuits.
In the prior art in which plural (m) clock generators such as a plurality of delay circuits are used in generating multiple-phase (m-phase) clock signals, as described in this patent reference, the amount of delay in the delay circuits fluctuates owing to changes in power-supply voltage and operating temperature, etc., if the delay circuits are constructed in an integrated circuit. Accordingly, a clock generator of m different phases requires the provision of delay circuits of m or more phases for the purpose of accommodating for the amount of fluctuation. As a consequence, control is complicated and it is necessary to finely adjust the amount of delay of the delay circuits.
Further, with the arrangement described in this patent reference, m (five in FIG. 8) clock generators are provided to deal with phase lead or lag of the clock. When the phase of a clock makes one full cycle, a smooth, seamless transition is desired with the same amount of delay. However, it is difficult to achieve a smooth, seamless transition owing to the fine adjustment of amount of delay and the use of m or more clock generators.
In a case where clocks of m different phases are generated by the ring oscillator 110, as shown in FIG. 8, this is technically feasible when the number of m-phase ring oscillators is small. In order to stabilize frequency, however, PLL (phase-locked loop) techniques are required. Further, if it is attempted to finely adjust phase resolution by increasing the number of clock generators for m different phases, the oscillating frequency of the ring oscillator will decline and the required frequency will no longer be obtained.
[Non-patent Document 1]
M. Sugawara, T. Ishibashi, K. Ogasawra, M. Aoyama, M. Zwerg, S. Glowinski, Y. Kameyama, T. Yanagita, M. Fukaishi, S. Shimoyama, T. Ishibashi and T. Noma, “1.5 Gbps, 5150 ppm Spread Spectrum SerDes PHY with a 0.3 mW, 1.5 Gbps Level Detector for Serial ATA”, Symposium on VLSI Circuits Digest of Technical Paper 5-3, FIG. 1, June/2002
[Non-patent Document 2]
S. Sidiropoulos and Mark Horowitz et. al., “A Semi-Digital DLL with Unlimited Phase Shift Capability and 0.08-400 MHz Operating Range,” ISSCC 1997 pp. 332-333
[Patent Document 1]
Japanese Patent Kokai Publication No. JP-P2001-148690A (pages 3 and 10 and FIGS. 3 and 11)
[Patent Document 2]
Japanese Patent Kokai Publication No. JP-A-7-235862 (pages 9, 10 and FIGS. 6, 7, 8 and 9)
[Patent Document 3]
Japanese Patent Kokai Publication No. JP-P2002-190724A (pages 8 and 9, FIG. 6)